Since a DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, stores information by the electric charge accumulated in a cell capacitor, the information is lost unless a refresh operation is periodically carried out. Therefore, Japanese Patent Application Laid-Open No. 2011-258259 discloses that a control device, which controls the DRAM, periodically issues a refresh command, which orders the refresh operation, to the DRAM. The refresh command is issued from the control device at a frequency that all word lines are certainly refreshed once in the period of one refresh cycle (for example, 64 msec).
However, depending on the history of access to memory cells, the information retention time of predetermined memory cells are reduced in some cases. Then, when the information retention time of the predetermined memory cells is reduced to less than the one refresh cycle, there has been a risk that part of the information may be lost even if the refresh command is issued at the frequency that all the word lines are refreshed once in the period of one refresh cycle.
In order to solve such a problem, recently, a technique which restores the electric charge with respect to the information-retention-time-reduced memory cells by utilizing the history of access to the memory cells has been studied. This technique is called target-row refresh.
Herein, in a case in which a defective word line is replaced by a redundant word line, erroneous operations may occur unless the target-row refresh operation is carried out in consideration of that. This is for a reason that actually-used (functional) redundant word lines and unused (non-functional) redundant word lines are mixed in the redundant word lines. More specifically, when the unused redundant word line is selected in a target-row refresh operation, for example, if micro short-circuit is present at the unused redundant word line or the memory cells connected thereto, there has been a risk that other data may be broken.